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19-2855; Rev 2; 4/05
2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning
General Description
The MAX8525 (VRM 10/VRD 10)/MAX8524 (VRM 9.1/ VRD 9.1) current-mode step-down controllers, the MAX8523 high-speed, dual-phase MOSFET gate driver, and the MAX8552 wide-input, single-phase MOSFET gate driver provide flexible, low-cost, low-voltage CPU core supplies. The MAX8523 and MAX8552 high-speed, high-current gate drivers allow operation at high switching frequencies to reduce external component size and cost for small-footprint, low-profile designs. Pin-selectable 2-, 3-, and 4-phase operation and master-slave 6and 8-phase operation provide output-current scalability for servers, workstations, desktops, desk notes, and networking applications. The switching frequency of the MAX8524/MAX8525 is adjustable from 150kHz to 1.2MHz, permitting loop bandwidths of up to 200kHz. Peak current-mode control provides fast transient response and reduces cost. A proprietary current-sharing scheme reduces current imbalance between phases to less than 5% at full load. The MAX8524/MAX8525 offer 0.4% initial accuracy and remote-sense functionality. Both controllers also feature programmable no-load offset and output-voltage positioning to adjust the output voltage as a function of the output current. The fast-active voltage positioning further reduces bulk output capacitors and cost. Current-mode control also simplifies compensation with a variety of capacitors by eliminating the output-filter double pole associated with voltage-mode controllers. Both devices are compatible with electrolytic, tantalum, polymer, and ceramic capacitors. Output current sensing eliminates issues associated with controllers that use high-side current sense and ensure stable and jitter-free operation. Temperature-compensated, lossless inductor current sense eliminates the need for a current-sense resistor and further reduces cost, while maintaining voltage-positioning accuracy and reducing power dissipation. The MAX8525 features control VID voltage transition for dynamic VID changes and eliminate both undervoltage and overvoltage overshoot. The PWRGD signal is accurate during VID code changes for the MAX8525 to avoid any false fault signal. Adjustable foldback current-limit and overvoltage protection provide for a robust design.
Features
VRD/VRM 10 (MAX8525) VRD/VRM 9.1 (MAX8524) Fastest Load-Transient Response Rapid-Active Average Current Sensing Better than 5% Current Balance Fastest Voltage Positioning 0.4% Initial Output-Voltage Accuracy Pin-Selectable 2-/3-/4-Phase Operation Master-Slave 6-/8-Phase Operation Differential Remote Voltage Sensing Dynamic VID Change (MAX8525) Adjustable, Foldback Current Limit Soft-Start and Soft-Stop Power-Good Output 150kHz to 1.2MHz Switching Frequency per Phase 28-Lead QSOP Package
MAX8524/MAX8525

Ordering Information
PART MAX8524EEI MAX8524EEI+ MAX8525EEI MAX8525EEI+ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 QSOP 28 QSOP 28 QSOP 28 QSOP
+Denotes lead-free package.
Pin Configurations
TOP VIEW
PWM3 1 PWM1 2 CS1+ 3 CS1_3- 4 CS3+ 5 VCC 6 GND 7 COMP 8 REF 9 ILIM 10 OSC 11 PWRGD 12 CLKO 13 CLKI 14 28 PWM2 27 PWM4 26 CS4+ 25 CS2_424 CS2+
MAX8525
23 RS+ 22 RS21 EN 20 VID4 19 VID3 18 VID2 17 VID1 16 VID0 15 VID5
Applications
Servers, Workstations Desktop Computers Desk Notes and LCD PCs Voltage-Regulator Modules High-End Switches and Routers
QSOP
Pin Configurations continued at end of data sheet. Functional Diagram appears at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
ABSOLUTE MAXIMUM RATINGS
REF, COMP, VID0 to VID5, OSC, CLKI, CLKO to GND ..........................................-0.3V to VCC + 0.3V RS+, RS-, ILIM to GND .................................-0.3V to VCC + 0.3V PWM_ to GND...............................................-0.3V to VCC + 0.3V EN, PWRGD, VCC to GND ........................................-0.3V to +6V CS1_3-, CS2_4-, CS_+ to GND ....................-0.3V to VCC + 0.3V Continuous Power Dissipation (TA = +70C) 28-Pin QSOP (derate 10.8mW/C above +70C).........860mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3k to GND, PWRGD = 100k to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = 0C to +85C, unless otherwise noted.)
PARAMETER GENERAL VCC Operating Range VCC UVLO Trip Level VCC Shutdown Supply Current VCC Standby Supply Current VCC Operating Supply Current Thermal Shutdown REFERENCE Reference Voltage Reference Load Regulation Reference Line Regulation Reference UVLO Trip Level SOFT-START Soft-Start Step Size Soft-Start Time per Step VOLTAGE REGULATION RS+ Input Bias Current RS- Input Bias Current VOUT Initial Accuracy VOUT Droop Accuracy COMP Output Current GMV Amplifier Transconductance GMV Amplifier Gain-Bandwidth Product VRS+ = 1.1V VRS- = 0.2V VID_ = 1.1V, TA = +25C VID_ = 1.1V (CS_+) = 1.125V (VO+) - (RS+) = 200mV -0.4 -0.6 5 385 2 5 0.1 0.1 1 1 +0.4 +0.6 A A % % A mS MHz Soft-start counts from EN rising (Note 1) 17 12.5 20 23 mV s IREF = 200A 100A < IREF < 500A 4.5V < VCC < 5.5V Rising edge, has 80mV typical hysteresis -0.05 1.74 1.84 2.0 - 0.4% 2.0 2.0 + 0.4% -0.05 +0.05 1.95 V % % V Rising Hysteresis VCC < 3.75V, VID_ = GND EN = 0V, VCC = 5.5V RS+ = 1.2V (no switching), set VID code for 1.100V Rising temperature, typical hysteresis = 15C 4.5 4.0 4.25 270 0.7 13 13 165 3 20 20 5.5 4.5 V V mV mA mA mA C CONDITIONS MIN TYP MAX UNITS
2
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3k to GND, PWRGD = 100k to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = 0C to +85C, unless otherwise noted.)
PARAMETER CURRENT-SENSE AMPLIFIERS CS_+, CS_- Input Bias Current Average Current-Limit Trip Level Accuracy ILIM Input Bias Current ILIM Default Program Level Peak Current-Limit Delay Time OSCILLATOR Oscillator Frequency Accuracy Switching Frequency Range (per Phase) Slave-Mode CLKI/Set Frequency Ratio Maximum CLKO Duty-Cycle Skew LOGIC INPUTS (EN) Input Low Level Input High Level Input Pullup Level Input Pullup Resistance LOGIC INPUTS (CLKI) Input Low Level Input High Level Input Pulldown Level Input Pulldown Resistance Input Low Level Input High Level Input Pullup Level Input Pullup Resistance Input Low Level Input High Level PWRGD OUTPUT Output Low Level Output High Leakage PWRGD Blanking Time IPWRGD = 4mA VPWRGD = 5.5V From EN rising, tracks CLKO 3 0.4 1 5 V A ms Internal pullup resistance VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V 0.8 10 MAX8525 LOGIC INPUTS (VID0-VID5) 0.4 V V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V Internal pulldown Internal pulldown VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V 1.6 VCC 15 20 50 3.6 GND 100 200 0.8 1.2 V V V k V V V k VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V Internal pullup Internal pullup 50 2.8 VCC 100 200 0.8 V V V k CLKO load < 50pF and ROSC = 40.2k 150 0.8 2 10 1200 4.0 % % kHz CS_+ = CS_- = 2V, RS+ = 0V VILIM = 1.5V, TA = +85C VILIM = 1.5V VILIM VCC - 0.2V -10 0.01 1 20 0.2 5 +10 1 A % A V ns CONDITIONS MIN TYP MAX UNITS
MAX8524/MAX8525
MAX8524 LOGIC INPUTS (VID0-VID4)
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3k to GND, PWRGD = 100k to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = 0C to +85C, unless otherwise noted.)
PARAMETER Output rising PWRGD Upper Threshold Output falling Output falling PWRGD Lower Threshold Output rising OVP PROTECTION MAX8524 output rising Output Overvoltage Trip Threshold, OVP Action MAX8525 output rising PWM, CKLO OUTPUTS Output Low Level Output High Level Source Current Sink Current Rise/Fall Times PWM Selection Threshold VCC = 4.5V to 5.5V 0.8 IPWM_ = -5mA IPWM_ = +5mA VPWM_ = VCC - 2V VPWM_ = 2V 4.5 0.1 4.9 84 83 10 2.3 3.1 0.4 V V mA mA ns V VID + 0.20 VID + 0.175 VID + 0.25 V VID + 0.225 VID 0.175 VID 0.125 VID + 0.075 VID 0.250 VID + 0.125 VID 0.200 V CONDITIONS MIN VID + 0.125 TYP MAX VID + 0.175 V UNITS
ELECTRICAL CHARACTERISTICS
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3k to GND, PWRGD = 100k to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER GENERAL VCC Operating Range VCC UVLO Trip Level VCC Shutdown Supply Current VCC Standby Supply Current VCC Operating Supply Current REFERENCE Reference Voltage Reference Load Regulation Reference Line Regulation Reference UVLO Trip Level IREF = 200A 100A < IREF < 500A 4.5V < VCC < 5.5V Rising edge, has 80mV typical hysteresis -0.05 1.74 2.0 0.5% 2.0 + 0.4% -0.05 +0.05 1.95 V % % V Rising, typical hysteresis 270mV VCC < 3.75V, VID_ = high EN = 0V, VCC = 5.5V RS+ = 1.2V (no switching), set VID code for 1.100V 4.5 4.0 5.5 4.5 3 20 20 V V mA mA mA CONDITIONS MIN TYP MAX UNITS
4
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3k to GND, PWRGD = 100k to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER SOFT-START Soft-Start Time per Step VOLTAGE REGULATION RS+ Input Bias Current RS- Input Bias Current VOUT Initial Accuracy CURRENT-SENSE AMPLIFIERS CS_+, CS_- Input Bias Current ILIM Input Bias Current OSCILLATOR Switching Frequency Range (per Phase) Slave-Mode CLKI/Set Frequency Ratio LOGIC INPUTS (EN) Input Low Level Input High Level Input Pullup Resistance LOGIC INPUTS (CLKI) Input Low Level Input High Level Input Pulldown Resistance Input Low Level Input High Level Input Pullup Resistance Input Low Level Input High Level VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V Internal pulldown VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V Internal pullup resistance VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V 0.8 1.7 10 20 0.4 3.6 50 200 0.8 1.2 V V k V V k V V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V Internal pullup 2.8 50 200 0.8 V V k 150 0.8 1200 4.0 kHz CS_+ = CS_- = 2V, RS+ = 0V VILIM = 1.5V 5 1 A A VRS+ = 1.1V VRS- = 0.2V VID_ = 1.1V -1 1 1 +1 A A % Soft-start counts from EN rising (Note 1) 17 23 s CONDITIONS MIN TYP MAX UNITS
MAX8524/MAX8525
MAX8524 LOGIC INPUTS (VID0-VID4)
MAX8525 LOGIC INPUTS (VID0-VID5)
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3k to GND, PWRGD = 100k to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER PWRGD OUTPUT Output Low Level Output High Leakage PWRGD Blanking Time IPWRGD = 4mA VPWRGD = 5.5V From EN rising, tracks CLKO Output rising PWRGD Upper Threshold Output falling Output falling PWRGD Lower Threshold Output rising OVP PROTECTION MAX8524 output rising Output Overvoltage Trip Threshold, OVP Action MAX8525 output rising PWM, CLKO OUTPUTS Output Low Level Output High Level PWM Selection Threshold IPWM_ = -5mA IPWM_ = +5mA VCC = 4.5V to 5.5V 4.5 0.8 3.1 0.4 V V V VID + 0.20 VID + 0.175 VID + 0.25 V VID + 0.225 VID 0.175 VID 0.125 VID + 0.075 VID 0.250 VID + 0.125 VID 0.200 V 3 VID + 0.125 0.4 1 5 VID + 0.175 V V A ms CONDITIONS MIN TYP MAX UNITS
Note 1: Total soft-start time equals the soft-start time per step times the VID voltage divided by 12.5mV. Note 2: Specifications at -40C are guaranteed by design.
6
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
Typical Operating Characteristics
(VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT AT 1.45V OUTPUT
MAX8524 toc01
OUTPUT VOLTAGE vs. LOAD CURRENT
VIN = 12V
MAX8524 toc02
OUTPUT LOAD TRANSIENT
MAX8524 toc03
100 90 80 70 EFFICIENCY 60 50 40 30 20 10 0 1 10 LOAD CURRENT (A) VIN = 5V VIN = 12V
1.200 1.175 1.150
80A IOUT 0A
1.125 VOUT 1.100 1.075 1.050 1.025 1.000 100 0 10 20 30 40 50 60 70 80 90 100 LOAD CURRENT (A) 10s POWERGOOD OUTPUT VOUT 50mV/div
4-PHASE ACTIVE CURRENT SHARING
MAX8524 toc04
DYNAMIC VID RESPONSE, 250mV STEP VOLTAGE
MAX8524 toc05
25
20 INDUCTOR CURRENT (A)
POWER-GOOD OUTPUT
15
10
PHASE 1 INDUCTOR CURRENT 10A/div OUTPUT VOLTAGE 200mV/div 0 10 20 30 40 50 60 70 80 90 100 LOAD CURRENT (A)
5
0 40s
SOFT-START WAVEFORMS AT 1.45V OUTPUT
MAX8524 toc06
SOFT-STOP WAVEFORMS AT 1.45V OUTPUT
MAX8524 toc07
ENABLE INPUT
POWERGOOD OUTPUT
ENABLE INPUT INPUT CURRENT 0.5A/div
INPUT CURRENT 0.5A/div OUTPUT VOLTAGE 0.5V/div
POWERGOOD OUTPUT 0A
OUTPUT VOLTAGE 0.5V/div IOUT = 0A
1ms
400s
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
Typical Operating Characteristics (continued)
(VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA = +25C, unless otherwise noted.)
SHORT-CIRCUIT AND RECOVERY WAVEFORMS
MAX8524 toc09 MAX8524 toc10
CURRENT-SENSE THRESHOLD vs. VILIM
POWERGOOD OUTPUT PHASE 1 INDUCTOR CURRENT 10A/div OUTPUT VOLTAGE 0.5V/div 2.010 1.400 1.200 1.000 VILIM (V) 0.800 0.600 0.400 0.200 0 1.990 0 10 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (A) -40 -20
REFERENCE VOLTAGE vs. TEMPERATURE
MAX8524 toc11
REFERENCE VOLTAGE (V)
2.005
2.000
1.995
1ms
0
20
40
60
80
100 120
TEMPERATURE (C)
REFERENCE VOLTAGE LOAD REGULATION
4900 4600 4300 4000 3700 3400 3100 2800 2500 2200 1900 1600 1300 1000 700 400 10
MAX8524 toc12
CLOCK FREQUENCY vs. ROSC
MAX8524 toc13
REFERENCE VOLTAGE (V)
2.001
2.000 0 100 200 300 400 500 REFERENCE LOAD CURRENT (A)
CLOCK FREQUENCY (kHz)
2.002
100 ROSC RESISTOR (k)
1000
CLOCK FREQUENCY vs. TEMPERATURE
5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) ROSC = 43.2k RISE (ns) ROSC = 105k
MAX8524 toc14
CLKO RISE AND FALL TIME vs. TEMPERATURE
10 9 8 7 6 5 4 RISE
MAX8524 toc15
10 9 8 7 6 5 4
FREQUENCY (MHz)
ROSC = 294k
3 2 1 0 -40 -20 0 20 40
FALL
3 2 1 0
60
80
100 120
TEMPERATURE (C)
8
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
Typical Operating Characteristics (continued)
(VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA = +25C, unless otherwise noted.)
INTERLEAVED 8-PHASE OPERATION: LX WAVEFORMS
MAX8524 toc16
8-PHASE ACTIVE CURRENT SHARING
MASTER PH1 MASTER PH2 MASTER PH3 MASTER PH4 SLAVE PH1 SLAVE PH2 SLAVE PH3 SLAVE PH4 INDUCTOR CURRENT (A)
MAX8524 toc17
8-PHASE OPERATION: DYNAMIC VID RESPONSE
MAX8524 toc18
25
20
POWERGOOD OUTPUT
15
10
PHASE 1 INDUCTOR CURRENT 10A/div OUTPUT VOLTAGE 200mV/div 26 52 77 101 126 150 40s
5
1s
0 0.193
LOAD CURRENT (A)
Pin Description
PIN MAX8524 1 2 3 4 5 6 7 MAX8525 1 2 3 4 5 6 7 NAME PWM3 PWM1 CS1+ CS1_3CS3+ VCC GND FUNCTION PWM Signal Output for Phase 3. Logic low during shutdown. PWM Signal Output for Phase 1. Logic low during shutdown Positive Input of the Output Current Sense of Phase 1. Connect to the inductor side of the output current-sense resistor. Common Negative Input of the Output Current Sense of Phases 1 and 3. Connect to the load side of the output current-sense resistors. Positive Input of the Output Current Sense of Phase 3. Connect to the inductor side of the output current-sense resistor. IC Supply Input. Bypass to GND with a ceramic capacitor of at least 1F. IC Ground. Single connection to system ground. Error-Amplifier Output. Connect to a tap in a resistor-divider from REF to GND to set the finite DC gain for active voltage positioning. Add a series RC network from COMP to GND to compensate the control loop. For 6- or 8-phase operation, connect COMP pins of two controllers together for active current sharing. 2.0V 0.4% Reference Output. Bypass REF to GND with a 2.2F low-ESR capacitor. REF can source 0.5mA for external loads. REF is alive when EN is low if VCC is above UVLO. Output Current-Limit Set. Connect to a tap of a resistor-divider from REF to GND to set the cycle-by-cycle average current-limit threshold. Current limit (per phase) = VILIM / (50 x RSENSE). Connect to VCC to set the default 20mV current-limit threshold. Internal Clock Oscillator Frequency-Set Input. Connect a resistor from OSC to GND to set the switching frequency. OSC must be connected to an external resistor even if the IC is used in slave mode. This pin is operational in shutdown if VCC is above UVLO. Open-Drain Power-Good Indicator. PWRGD pulls low until the output voltage is in regulation. PWRGD is low in shutdown and during UVLO.
8
8
COMP
9
9
REF
10
10
ILIM
11
11
OSC
12
12
PWRGD
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
Pin Description (continued)
PIN MAX8524 MAX8525 NAME FUNCTION Clock Synchronization Output for Master-Mode Operation. Connect CLKO of the master controller to CLKI of the slave controller. CLKO is active when EN is low, if VCC is above UVLO to permit synchronized slave startup. CLKO is connected to the internal oscillator in both master and slave mode. Clock Synchronization Input. Connect CLKI to CLKO of the master controller for interleaved dual controller systems or to an external synchronization clock. Internal 100k pulldown to GND permits floating this pin. See the Paralleling Operation section for detailed clocking operation. DAC Code Input. The MAX8524 has a 15k internal pullup resistor to VCC. The MAX8525 requires an external pullup resistor. DAC Code Input. The MAX8525 requires an external pullup resistor. Connect to VCC for the MAX8524. No Connection Enable Input, Active High. Pulls up to VCC through an internal 100k resistor when UVLO is satisfied. Pull low with an external open-drain or open-collector input to shut down the controller. For master/slave operation, the EN pins of the MAX8524/MAX8525 controllers should be connected together. Output-Voltage Remote-Sense, Negative Input. Connect to GND directly at the load. Output-Voltage Remote-Sense, Positive Input. Connect to VOUT+ directly at the load. Positive Input of the Output Current Sense of Phase 2. Connect to the inductor side of the output current-sense resistor. Short CS4+ to CS2_4- for 2-phase operation. Common Negative Input of the Output Current Sense of Phases 2 and 4. Connect to the load side of the output current-sense resistors. Positive Input of the Output Current Sense of Phase 4. Connect to the inductor side of the output current-sense resistor. Short CS4+ to CS2_4- for 2-, 3-, or 6-phase operation. PWM Signal Output for Phase 4. Connect this pin to VCC for 2-, 3-, or 6-phase operation. Logic low during shutdown. PWM Signal Output for Phase 2. Connect this pin to VCC for 2-phase operation. Logic low during shutdown.
13
13
CLKO
14
14
CLKI
15-19 -- 20
16-19 15 --
VID0-VID4 VID5 N.C.
21
21
EN
22 23 24 25 26 27 28
22 23 24 25 26 27 28
RSRS+ CS2+ CS2_4CS4+ PWM4 PWM2
Detailed Description
The MAX8524/MAX8525 are synchronous, scalable 2-/ 3-/4-phase, current-mode, step-down controllers. The MAX8524/MAX8525 can be used to implement either an embedded VRD design or a voltage regulator module (VRM) design with external MOSFET driver, such as the MAX8523. The switching frequency of each phase can be set from 150kHz to 1.2MHz, permitting control bandwidth of up to 200kHz. The 5MHz gain-bandwidth product of the voltage-error amplifier ensures sufficient loop gain for most applications. In VRM applications, current bal10
ance between modules is within 5% at full load, maximizing the benefits of multiphase operation. Lossless inductor current sensing with temperature compensation can be used to reduce power dissipation while maintaining droop accuracy. The MAX8524/MAX8525 controllers can be configured for 3-phase or 2-phase VRD or VRM applications by connecting one or two PWM pin(s) to the logic-supply pin (VCC). In these modes, internal phasing is automatically adjusted for optimal ripple cancellation. The CLKI (clock in) and CLKO (clock out) features provided by the MAX8524/MAX8525 permit true 6- or 8-phase interleaved operation when two MAX8524/MAX8525 con-
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
Table 1. VID Programmed Output Voltage (VRM 10.0)
VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VOUT 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 OFF OFF 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VOUT 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.5875
trollers are utilized, further reducing input and output ripple current. In 4-phase operation, the effective switching frequency is 0.6MHz to 4.8MHz. For 8-phase operation, the effective switching frequency is 1.2MHz to 9.6MHz. The MAX8525 includes a 6-bit DAC (Intel VRM 10.0 compliant) and the MAX8524 includes a 5-bit DAC (Intel VRM 9.1 compliant), both able to achieve 0.4%
initial voltage accuracy. The power-good signal is accurate during VID code changes for the MAX8525 to avoid any fault signal due to the output voltage change requested by the CPU. The MAX8524/MAX8525 also include programmable no-load offset and output-voltage positioning to adjust the output voltage as a function of the output current.
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
Table 2. VID Programmed Output Voltage (VRM 9.1)
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT 1.850 1.825 1.800 1.775 1.750 1.725 1.700 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 Shutdown
Table 3. Clock Frequency Setting vs. Switching Frequency and Number of Phases
NO. OF PHASES 2 3 4 6 8 PIN CONNECTIONS PWM2 = PWM4 = VCC PWM4 = VCC -- PWM4 = VCC -- fCLKO 4 x fSW 3 x fSW 4 x fSW 3 x fSW 4 x fSW
slave mode. A 1% resistor is recommended for the ROSC to maintain good frequency accuracy, and ROSC should be placed as close as possible to the OSC pin.
Voltage Reference (REF)
A precision 2V reference is provided by the MAX8524/MAX8525 at the REF pin. REF is capable of sourcing up to 500A for external loads. REF stays alive when EN is low and while VCC is above UVLO. Connect a 0.22F ceramic capacitor from REF to GND. The capacitor should be placed as close to the REF pin as possible. An internal REFOK monitors the reference voltage. The reference voltage must be above the REFOK threshold of 1.85V to activate the controller. The controller is disabled if the reference voltage falls below 1.81V.
Output Current Sensing (CS_+, CS_-)
The output current of each phase is sensed differentially with a shared common return for each phase pair. A low offset voltage and high-gain (50V/V) differential current amplifier at each phase allow low-resistance current-sense resistors to be used to minimize power dissipation. Sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output inductor. Using the DC resistance, RDC, of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of RDC must be accounted for in the output-voltage droop-error budget. An RC filtering network is needed to extract the current information from the output inductor, as shown in Figure 1. The time constant of the RC network is governed by equation 1: RC = L RDC (Eq 1)
Clock Frequency (OSC)
The clock frequency of the MAX8524/MAX8525 is set by an external resistor from OSC to ground. After selecting the switching frequency per phase, fSW, and the number of phases, using Table 3, select the clock frequency. For 6- or 8-phase operation, connect an external resistor to OSC of both master and slave controllers even if the MAX8524/MAX8525 is operated in
12
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
L RDC VRDC = RDC x IOUT R C IOUT
C=
ESL RS x R
(Eq 2)
CS_+
CS_-
where ESL is the equivalent series inductance of the current-sense resistor, RS is the value of the currentsense resistor, and C is the value of the compensation capacitor. For example, a 1m 2025-package sense resistor has an ESL of 1.6nH.
RDC IS THE INDUCTOR DC RESISTANCE.
Figure 1. Inductor RDC Current Sense
ESL RS VRS = RS x IOUT R C IOUT
Output Current-Limit and Short-Circuit Protection (ILIM)
The MAX8524/MAX8525 provide a cycle-by-cycle current limit to control the average output current as programmed by the user at the ILIM pin. This approach is insensitive to input-voltage variation and inductor tolerance. Once the current-limit threshold is exceeded, the duty cycle is terminated immediately and the output inductor current starts to ramp down. At the next switching cycle, the PWM pulse is skipped if the output inductor current is still above the current-limit threshold. The current-limit threshold is adjustable over a wide range by connecting a resistor-divider from the REF pin to GND with the center tap connected to ILIM. Connecting ILIM to VCC sets the default current threshold to 20mV at the current-sense resistor. The MAX8524/MAX8525 offer current foldback protection under soft-start and overload conditions. This feature allows the VRM to safely operate under short-circuit conditions and to automatically recover once the short-circuit condition is removed. Once the output voltage falls below the low PWRGD threshold, the foldback current threshold is set to half the currentlimit threshold.
CS_+
CS_-
ESL IS THE PARASITIC INDUCTANCE OF PRECISION CURRENT-SENSE RESISTOR.
Figure 2. Current-Sense Resistor
where L is the inductance of the output inductor. For 20A or higher current-per-phase applications, the DC resistance of commercially available inductors is about 1m, as shown in Table 4. To minimize current-sense error due to the bias current at current-sense pins, choose R less than 2k (Figure 1). Determine the value for C from equation 1. Choose the capacitor with 5% tolerance and the resistor with 1% tolerance. Temperature compensation is recommended for this current-sense scheme. See the Loop Compensation and Output-Voltage Positioning section for detailed information. When a current-sense resistor is used for more accurate output-voltage positioning, similar RC filtering circuits should be used to cancel the equivalent series inductance of the current-sense resistor, as shown in Figure 2. Using criteria similar to that stated in the previous paragraph, the value of C can be determined by equation 2:
Output Voltage Differential Sensing (RS+, RS-)
The MAX8524/MAX8525 feature differential output-voltage sensing to achieve the highest possible output accuracy. This allows the controllers to sense the actual voltage at the load, so the controller can compensate for losses in the power output and ground lines.
Table 4. Output Inductor List
MANUFACTURER AND PART NO. RDC (m) BI Technologies HM73-40R50 0.5H/50A 0.78 (typ) 1.0 (max) Panasonic ETQP1H0R6BFA 0.6H/30A 0.9 (max) Sumida CDEP149(H) 0.45H/32A 0.9 (typ) 1.1 (max) Coiltronics HC2-0R68 0.68H/50A 0.6 (max)
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
TO POSITIVE OUTPUT OF VRM R1 50 R3 100
MAX8524/ MAX8525
RS+
TO REMOTE-SENSE LOCATION R4 100 RSR2 50 C1 470pF C1 470pF
TO POWER GROUND OF VRM
resistor, RE, from the COMP pin to GND (RE = RU//RB). The value of RE is determined by the amount of droop required at full load, which is specified as the output impedance or the load line in Intel VRM specifications. According to the Intel VRM specifications, the output voltage at no load cannot exceed the voltage specified by the VID code, including the initial set tolerance, ripple voltage, and other errors. Therefore, the actual output voltage should be biased lower to compensate for these errors. Connect a resistor-divider, RU and RB, from REF to GND, with the tap connected to COMP, to set the offset voltage. For 6- or 8-phase operations, connect COMP pins of the two controllers together for active current sharing.
Figure 3. Recommended Filtering for Output-Voltage Remote Sensing
Dynamic VID Change (MAX8525 Only)
The MAX8525 offers the ability to dynamically change the VID inputs while the controller is operating (on-thefly, or OTF). This feature allows the processor to adjust its core voltage in a 250mV window. The MAX8525 output voltage changes in 12.5mV steps when a VID change is detected. The VID inputs of the MAX8525 comply with Intel's 400ns logic-skew timing specifications to prevent false code changes. Once the timer expires, the controller starts to change the DAC output. Figure 4 shows the output voltage step during a VID OTF event. The MAX8525 controller accepts both step-by-step changes of VID inputs or all-at-once VID inputs changes. For all-at-once VID input changes, the output-voltage slew rate is the same as 12.5mV per step and 2s duration.
Traces from the load point back to RS+ and RS- should be routed close to each other and as far away as possible from noise sources (such as inductors and high di/dt traces). Use a ground plane to shield the remotesense traces from noise sources. To filter out commonmode noise, RC filtering is recommended for these pins as shown in Figure 3. For VRD applications, a 100 resistor with a 470pF capacitor should be used. For VRM applications, additional 50 resistors should be connected from these pins to the local outputs of the converter before the VRM connector. This avoids excessive voltage at the CPU in case the remote-sense connections get disconnected.
Loop Compensation (COMP)
During a load transient, the output voltage instantly changes due to the ESR of the output capacitors by an amount equal to their ESR times the change in load current (VOUT = -RESR_CO x ILOAD). The voltagepositioning method allows better utilization of the output regulation window, resulting in fewer output capacitors. The MAX8524/MAX8525 employ rapid-active average scheme, a proprietary current-mode architecture that adjusts the output current based on instantaneous output voltage, resulting in fast voltage positioning. The voltage-error amplifier consists of a high bandwidth and high-accuracy transconductance amplifier (GMV). See the Functional Diagram. The negative input of the transconductance amplifier is connected to the output of the remote-voltage differential amplifier, and the positive input is connected to the output of an internal DAC controlled by VID inputs. The DC gain of the transconductance amplifier is set to a finite value to achieve fast output-voltage positioning by connecting an equivalent
Paralleling Operation (CLKI and CLKO)
Two MAX8524/MAX8525s can be connected together to generate 6-phase or 8-phase core supplies. In this configuration, one MAX8524/MAX8525 serves as a master and the other serves as a slave. Connect the CLKI pin of the slave controller to the CLKO pin of the master controller. Interleaved operation is achieved by synchronizing the master controller to the CLKO rising edge and the slave controller to the CLKO falling edge. Figure 5 shows the clock timing between the phases of both master and slave controllers.
2-Phase and 3-Phase Operation Selection (PWM3 and PWM4)
The MAX8524/MAX8525 can operate in 2-, 3-, and 4-phase operation. Connect PWM4 to VCC for 2-, 3-, or 6-phase operation. Also connect PWM2 to VCC for 2-phase operation. All PWM outputs are held low during shutdown.
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
Power-Good Output (PWRGD)
MAX8524 fig04
POWER-GOOD OUTPUT INDUCTOR CURRENT OF PH1
PWRGD is an open-drain output that is pulled low when the output voltage rises above the PWRGD upper threshold or falls below the PWRGD falling threshold. PWRGD is held low in shutdown, VCC < UVLO, and during soft-start conditions. For logic-level output voltages, connect an external pullup resistor between PWRGD and the logic power supply. A 100k resistor works well in most applications.
OUTPUT VOLTAGE 0.2V/div
UVLO, Output Enable (EN), and Soft-Start
When the IC supply voltage (V CC ) is less than the UVLO threshold, all PWM outputs are held low and most internal circuitry is shut down to reduce the quiescent current. When EN is released and VCC > UVLO, the internal 100k resistor pulls EN to VCC and softstart is initiated. During soft-start, the output of the internal DAC ramps up at 12.5mV per step. For 6- or 8-phase operation, connect EN of two MAX8524/ MAX8525s together and drive it by an open-drain signal, as shown in Figure 6.
40s
Figure 4. Output-Voltage Waveform During VID On-the-Fly Change with Load Transients
EIGHT-PHASE OPERATION MASTER IC PHASE CLOCK CLKOUT PHASE 1 PHASE 2 PHASE 3 PHASE 4
Output Overvoltage Protection (OVP)
When the output voltage exceeds the regulation voltage by 225mV for the MAX8524 or 200mV for the MAX8525, all PWM outputs are pulled low and the controller is latched off. To discharge the output voltage, the MOSFET drivers must keep the low-side MOSFETs on and high-side MOSFETs off. The MAX8523 dualphase and the MAX8552 single-phase MOSFET drivers fulfill this requirement. The latch condition can only be cleared by cycling the input voltage (VCC).
Thermal Protection
SLAVE IC PHASE CLOCK
CLKIN PHASE 1 PHASE 2 PHASE 3 PHASE 4
The MAX8524/MAX8525 feature a thermal-fault-protection circuit. When the junction temperature rises above +150C, an internal thermal sensor activates the shutdown circuit to hold all PWM outputs low to disable switching. The thermal sensor reactivates the controller after the junction temperature cools by 15C.
Design Procedure
Setting the Switching Frequency
The switching frequency determines the switching loss and the size of the power components. Higher switching frequency results in smaller external components and more compact design. However, switching loss and magnetic core loss are directly proportional to the switching frequency. Select a switching frequency as a tradeoff of the efficiency and size. The clock frequency can be selected from Table 3.
Figure 5. Clock Relationships Between the Master and Slave Controllers
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
VID0 INPUT VID1 INPUT VID2 INPUT VID3 INPUT VID4 INPUT VID5 INPUT
VID0 VID1 VID2 VID3 VID4 VID5
MASTER
CLKO REF RS+ RS-
VID0 VID1 VID2 VID3 VID4 VID5 CLKI REF
SLAVE
REMOTE-SENSE INPUT
MAX8524/ MAX8525
COMP
MAX8524/ MAX8525 RS+
COMP RS-
EN
EN
EN INPUT
Figure 6. Master and Slave Controller Connections
See the Clock Frequency vs. ROSC graph in the Typical Operating Characteristics section for the relationship between the clock frequency and the value of the frequency-setting resistor, ROSC. The value of ROSC for a given clock frequency can also be approximated from equation 3: ROSC = 277.704 x fOSC(MHz)-1.197 k (Eq 3)
where fSW is the switching frequency, IOUT_MAX is the maximum-rated output current, D is the duty ratio, and VOUT is the output voltage at a given VID code. Check the output-inductance ripple current for the ripple voltage it produces across the output capacitor ESR. For an n-phase VRM converter, the output ripple voltage, VRIPPLE, can be calculated using: VRIPPLE = VOUT x RESR _ CO x (1 - (N x D)) fSW x L
(Eq 5)
Output Inductor Selection
Output inductance is set by the desired amount of inductor current ripple (LIR) and the slew rate of the inductor current during a load transient. A larger inductance value minimizes output ripple current and increases efficiency but slows down the current slew rate. For the best tradeoff of size, cost, and efficiency, an LIR of 30% to 60% is recommended (LIR = 0.3 to 0.6). Choose LIR close to the high end when more phases are used. The inductor value is determined from: L VOUT x (1 - D) x N H LIR x fSW x IOUT _ MAX (Eq 4)
For ripple voltage estimate, it is safe to replace RESR_CO with RO, the VRM output impedance. If the output ripple voltage is not satisfied, a larger value of output inductance should be chosen. The selected inductor should have the lowest possible DC resistance and the saturation current should be greater than the peak inductor current, IPEAK. IPEAK is found from: IPEAK = IOUT _ MAX (2 + LIR) 2xN
(Eq 6)
When the DC resistance of the output inductor is used for current sensing, the range of DC resistances is limited by the following constraints:
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning
RDC and RDC N 50 x IOUT _ MAX x (2 + LIR) 5xN 50 x IOUT _ MAX x (2 + LIR)
(Eq 7)
(Eq 8)
and ceramic capacitors, should be used to avoid large voltage transients at the input during a large step load change at the output. The capacitors' ripple-current specifications provided by the manufacturer should be carefully reviewed. Additional small-value low-ESL ceramic capacitors (1F to 10F/16V) can be used in parallel to reduce the high-frequency ringing.
MAX8524/MAX8525
Power MOSFET Selection
MOSFET power dissipation depends on the gate-drive voltage (VG), the on-resistance (RDSON), the total gate charge (QGT), and the gate threshold voltage (VTH). The supply voltage range for MOSFET drivers (MAX8523) is from 4.5V to 6.5V. With VGATE < 10V, logic-level threshold MOSFETs are recommended. Power dissipation in the high-side MOSFET consists of two parts: the conduction loss and the switching loss. The conduction loss for each high-side switch can be calculated from equation 12:
PCOND _ HS = D x x I2OUT _ MAX 2 N2 LIR2 x 1 + 12 (Eq 12)
Output Capacitor Selection
In most cases, selection of the output capacitor is dictated by the ESR requirement to meet the core-supply transient responses. The target equivalent series resistance is RESR_CO = RO. The minimum output capacitance, CO(min), based on the energy balance, is then calculated from: CO (min) L x IOUT _ MAX 1 x 2 N x RO x VOUT (Eq 9)
There is also an upper limit on the amount of output capacitance to meet the OTF VID change requirement. Too much output capacitance may prevent the output voltage from reaching the new VID output voltage within the OTF time window: CO (max) (ILIM - IOUT _ MAX )2 x t OTF VOTF (Eq 10)
RDSON _ HS MHS
where tOTF is the time window to reach VOTF, the OTF voltage steps. If CO(max) is less than CO(min), the system does not meet the VID OTF specification. Combinations of different types of capacitors, such as SPCAPs, POSCAPs, or low-ESR aluminum electrolytic capacitors may be needed to achieve the required RESR_CO and the output capacitance simultaneously. If the combination cannot be reached, the output inductance must be adjusted.
where MHS is the number of MOSFETs in parallel for each high-side switch. Total high-side conduction loss equals the number of phases times PCOND_HS. Switching loss is the major contributor to the high-side MOSFET power dissipation due to the hard switching transition every time it turns on. The switching loss can be found from the following:
PSW _ HS = 2 x VIN x IOUT _ MAX N x RGATE x QMILLER VD - VTH (Eq 13)
x fSW x MHS
Input Capacitor Selection
The input capacitor reduces the peak current drawn from the power source and reduces the noise and voltage ripple on the input caused by the circuit's switching. The input capacitors must meet the ripple current requirement, IRMS, imposed by the switching currents as defined by equation 11: IRMS = D x IOUT _ MAX x 1 -1 Nx D (Eq 11)
where VD is the gate-drive voltage and RG is the total gate resistance including the driver's on-resistance from the MAX8523 (0.8) and the MOSFET's gate resistance. QMILLER is the MOSFET's Miller charge, which can be found in the MOSFET's data sheet. For a logic-level power MOSFET, the gate resistance is about 2. Note that adding more MOSFETs in parallel at the high-side switch increases the switching loss. Smaller gate charge and lower gate resistance usually result in lower switching loss. The low-side MOSFET power dissipation is mostly attributed to the conduction loss. Switching loss is negligible due to the zero voltage switching at turn-on and body diode clamp at turn-off. Power dissipation in the
17
Use the minimum input voltage to calculate the input ripple current. Low-ESR capacitors, such as low-ESR aluminum electrolytic capacitors, polymer capacitors,
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
low-side MOSFETs of each phase can be calculated from the following equation:
PCOND _ LS = (1- D) x x I2OUT _ MAX 2 N2 LIR2 x 1 + 12 (Eq 14)
RDSON _ LS MLS
where GM is the transconductance (2ms). A capacitor, CC, must be connected from COMP to ground to roll off the gain at high frequency. The capacitor value can be found from the following equation once the output capacitor's ESR zero frequency is known to obtain firstorder rolloff at zero across frequency: CC = RESR _ CO x CO RE (Eq 18)
where RDSON_LS is the on-resistance of the low-side MOSFET and MLS is the number of MOSFETs in parallel for the low-side switch. Total power dissipation for the low-side switches equals the number of phases times the low-side conduction loss of each phase. Even though the switching loss is insignificant in the low-side MOSFETs, RDSON is not the only parameter that should be considered in selecting the low-side MOSFET. Large Miller capacitance (CRSS) could turn on the low-side MOSFETs momentarily when the drain-to-source voltage goes high at fast slewing rates if the driver cannot hold the gate low. The ratio of C RSS/CISS should be less than 1/10th for the low-side MOSFETs to avoid shoot-through current due to momentary turn on of the low-side switch. The gate-driver power dissipation is also important. The MAX8523 is a 0.8/0.6 dual-channel driver, whereas the MAX8552 is a 0.8/0.6 single-channel driver. Power dissipation in each driver is given by:
2 x fSW x (MLS x QG _ LS + PDRIVER = VD x (Eq 15) MHS x QG _ HS ) + ICC
where RESR_CO is the total equivalent series resistance and CO is the total capacitance of the output capacitors, respectively. RE is the parallel equivalent resistance of RU and RB.
Setting the Current Limit
Current-limit threshold sets the maximum available output DC current. To meet the OTF operation, the output current limit, ILIM, should be set at least 15% higher than the maximum rated output current, IOUT_MAX. The voltage at ILIM and the value of the current-sense resistor or the DC resistance of the output inductors set the current-limit threshold: I VILIM = 50 x RSENSE x LIM N for the resistor current sensing and: I VILIM = 50 x RDC x LIM N (Eq 20) (Eq 19)
where I CC is the supply current of the MAX8523. Ensure the power loss does not exceed the package power dissipation.
Loop Compensation and Output-Voltage Positioning
Once the current-sense resistance (RSENSE), the output impedance (RO), and the output offset voltage (VOS) are known, the values of RU and RB are calculated from equations 16 and 17: 1 (Eq 16) RU = GM NRO - VOS 2 RSENSE x 50
B=
for DC resistance of the output inductor current sensing. In equation 22, the value of RDC at the high ambient temperature must be used to guarantee the rated output current. VILIM can be set by connecting ILIM to a resistor-divider from REF to GND. Select resistors R26 and R27 from the schematics in Figure 7 so the current through the divider is at least 10A: R26 + R27 200k (Eq 21)
A typical value for R27 is 100k; then solve for R26 using: R26 = R27 x 2 - VILIM VILIM (Eq 22)
1 GM 2 NRO 1 + VOS 6 RSENSE x 50 20 x 10
(Eq 17)
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2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning
Applications Information
PC Board Layout Guidelines
A properly designed PC board layout is important in any switching DC-DC converter circuit. If possible, mount the MOSFETs, inductors, input/output capacitors, and current-sense resistor on the top side of the PC board. Connect the ground for these devices close together on a power ground plane. Make all other ground connections to a separate analog ground plane. Connect the analog ground plane to power ground at a single point. To help dissipate heat, place high-power components (MOSFETs and inductors) on a large PC board area, or use a heat sink. Keep high-current traces short, wide, and tightly coupled to reduce trace inductances and resistances. Also, make the gate-drive connections (DH_ and DL_) short, wide, and tightly coupled to reduce EMI and ringing induced by high-frequency gate currents. Use Kelvin-sense connections for the current-sense resistors. All signal traces of the current sense and the remote-voltage sense should be tightly coupled and as far away as possible from the inductors and other switching noise sources. Use the ground plane to shield the current-sense traces and the feedback from noise sources. Place the REF capacitor, the VCC capacitor, the currentsense decoupling capacitors, and the remote-sense decoupling capacitors as close to the MAX8524/ MAX8525 as possible. For an example PC board layout, refer to the MAX8525 evaluation kit.
MAX8524/MAX8525
Chip Information
TRANSISTOR COUNT: 9021 PROCESS: BiCMOS
Pin Configurations (continued)
TOP VIEW
PWM3 1 PWM1 2 CS1+ 3 CS1_3- 4 CS3+ 5 VCC 6 GND 7 COMP 8 REF 9 ILIM 10 OSC 11 PWRGD 12 CLKO 13 CLKI 14 28 PWM2 27 PWM4 26 CS4+ 25 CS2_424 CS2+
MAX8524
23 RS+ 22 RS21 EN 20 N.C. 19 VID4 18 VID3 17 VID2 16 VID1 15 VID0
QSOP
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19
MAX8524/MAX8525
2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning
Figure 7. Typical Application Circuit for VRM 10 Using a Sense Resistor for Output Current Sensing and 8-Pin SO MOSFET Packages
INPUT 10V TO 13.2V J1-1 J1-2 J1-3 L1 0.6H RS1 1m VDD = 6.5V 6 4 4 PV1 BST1 13 PV2 DH1 3 1 1 CS1+ VIN+ R9 3.3 5 6 4 C14 0.22F 1 1 R S2 1m N4 3 2 N14 3 2 L2 0.6H 4 8 7 6 8 7 5 CS1_3C13 0.22F 4 4 N3 3 2 N2 3 2 R1 24 C9 33nF R12 10 1 2 5 6 8 7 8 7 5 6 R8 3.3 1 1 1 2 2 N1 3 N13 3 2 4 6 3 D1 5 8 7 8 7 5 3 KA317MR U4 1 R5 402 C20 2.2F C19 2.2F C21 2.2F 16V REF R6 1.3k 2 C1 10F 25V C2 10F 25V
20
U2 MAX8523 LX1
7 VCC R27 10 100k C18 0.1F R15 OPEN 8 DLY BST2 DH2 9 PWM1 LX2 PWM2 DL2 1 1 12 R2 24 CS3+ 5 6 4 5 6 4 8 7 N6 3 2 8 7 N5 3 2 C10 33nF 14 10 15 2 6 VCC PWM1 5 DL1 6 PG1 11 PG2 D3 R18 OPEN R26 28.3k
1
3
2
R13 10 5%
ILIM
16
C3 10F 25V
C4 10F 25V
C22 1F 10V
R16 100k 12 PWRGD VID4 VID3 COMP VID1 VID0 CLKI 9 REF VDD = 6.5V 3 5 6 5 6 8 7 D2 8 7 C29 3.3nF AGND 26 21 EN 25 5 3 4 CS1_37 C17 0.1F PWM2 BST2 11 OSC 9 PWM1 PWM2 10 PWM4 27 DH2 LX2 14 DL2 12 16 15 C16 0.22F 5 6 28 DLY R17 OPEN 8 R11 3.3 C28 3.3nF 5 DL1 VCC MAX8523 6 PG1 PG2 11 5 6 R14 10 CS1+ PV2 CS3+ 13 DH1 CS2_42 C15 0.22F PV1 5 6 4 BST1 1 24 CS2+ 1 2 CS4+ R10 3.3 8 7 CLKO 13 14 VIN+ C5 10F 25V C6 10F 25V 16 J1-55 17 J1-8 VID2 18 J1-56 19 J1-7 20
U1
PWM3 VID5 15 J1-54 J1-6
1
J1-10 VCC-PWRGD
MAX8525
OUTPUT 0.8375V TO 1.6V, 80A VO+ C30-C39 390F/2V SPCAPS VOC40-C45 470F/6V SPCAPS
8
R29 6.81k
R28 6.81k
R22 348
C23 680pF
R25 5.11k
R24 28.7k
C24 0.22F 7
4
N7 3 12
4
J1-53 OUTEN C25 470pF
N15 3 12 5
L3 0.6H 6 8 7
RS1 1m R3 24
VOUT
CS4+ CS2+ CS2_4CS3+ CS1+ CS1_3-
U3
LX1 3
4
1
R19 50 23 RS+ C26 470pF 22 RS-
N8 3 2
4
1
N9 3 2
C11 33nF CS2+ VIN+ 5
J1-52 V0_SEN+
R20 100
J1-11 V0_SEN-
R21 100
8 7
6
8 7
C7 10F 25V
C8 10F 25V
J1-13 J1-15 J1-17 J1-19 J1-21 J1-23 J1-25 J1-27 J1-29 J1-31 J1-32 J1-34 J1-36 J1-38 J1-40 J1-42 J1-44 J1-46 J1-48
J1-14 J1-16 J1-18 J1-20 J1-22 J1-24 J1-26 J1-28 J1-30 J1-33 J1-35 J1-37 J1-39 J1-41 J1-43 J1-45 J1-47 J1-49 J1-50
R18 50
C27 470pF
4
N10 3 12
4
N16 3 12 5 6
R23 200k
L4 0.6H
RS2 1m
4
1
8 7 N11 3 2
4
1
8 7 N12 3 2
R4 24 CS4+
C12 33nF CS2_4-
______________________________________________________________________________________
L1-L4: PANASONIC, N1, N4, N7, N10, N13-N16: IRF7811W N2, N3, N5, N6, N8, N9, N11, N12: IRF7822
NOTE: C30-C45 SELECTED FOR VRM 10 TRANSIENT RESPONSE SPECIFICATIONS AT 1.2V OR HIGHER OUTPUT.
VIN+ 3 KA317MR U4 1 4 PV1 BST1 13 PV2 DH1 C13 0.22F CS1+ VIN+ CS1_3C3 10F 25V C4 10F 25V L2 0.29H N3 C14 0.22F N4 R2 24 CS3+ C10 0.033F C30-C39 330F/10m SPCAPS N2 R1 24 C9 0.033F R12 10 7 R27 27k C18 0.1F 2 1 DH2 9 PWM1 LX2 PWM2 DL2 12 14 10 15 15 20 19 18 17 16 14 VDD = 6.5V 3 C29 0.015F AGND 26 21 EN 25 5 3 4 CS1_37 C17 0.1F 8 C28 0.015F 28 27 DH2 9 10 PWM1 PWM2 LX2 14 DL2 12 CS1+ R14 10 CS3+ CS2_4PV2 13 24 CS2+ DH1 CS4+ 4 PV1 BST1 1 2 LX1 3 C15 0.22F N6 R3 24 CS2+ VIN+ R11 0 DLY BST2 PWM4 11 OSC R23 95k 16 15 C16 0.22F N8 R4 24 C12 0.033F C7 10F 25V N7 L4 0.29H C8 10F 25V RS4 1m C11 0.033F R10 0 1 2 D2 VIN+ C5 10F 25V N5 L3 0.29H C6 10F 25V RS3 1m BST2 8 DLY VCC R9 0 10 ILIM VCC PWM1 5 DL1 6 PG1 11 PG2 3 MAX8523 LX1 1 2 1 2 R S1 1m R5 249 C20 2.2F C19 2.2F R8 0 N1 L1 0.29H C21 2.2F 16V REF R6 1.02k 2 VDD = 6.5V 3 D1 C1 10F 25V C2 10F 25V
1
U2
3 2 R13 10 5% 6 R18 OPEN R26 10k
D3
16
C22 1F 10V R16 100k 12 PWRGD VID4 VID3 COMP VID1 R22 29k CLKI 9 REF CLKO 13 C24 0.22F 7 VID0 VID2
U1
PWM3 VID5
R S2 1m
VOUT = 80A VO+ VO-
J1-10 VCC-PWRGD
MAX8525
8
R24 6.8k
R15 11.9k
C23 680pF
OUTEN
VOUT C25 470pF R20 100 23 RS+ PWM2 22 RSC26 470pF R21 100 C27 470pF
Figure 8. 600kHz Application Circuit with Direct MOSFETs for Compact VRM 10 Design
CS4+ CS2+ CS2_4CS3+ CS1+ CS1_3-
U3
R19 50
V0_SEN+
5 DL1 VCC MAX8523 6 PG1 PG2 11
V0_SEN-
R18 50
CS4+ L1-L4: TDK, SPM12535T-R23M300 N1, N3, N5, N7: IRF7801 N2, N4, N6, N8: 2XIRF7822, EACH
2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning
MAX8524/MAX8525
______________________________________________________________________________________
CS_4-
21
2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525
Functional Diagram
UVLO REFOK EN 100k MUX 0 div 2 RUN S PWRGD PWRGD CURRENT FOLDBACK AND FAULT LOGIC PWM S/R PWM1 INTERNAL CLOCK div 2/3/4 OSC 0.9MHz TO 9.6MHz OSCILLATOR
CLKI
SYNC DETECT 1
AND
VCC
CLKO
0.45MHz TO 4.8MHz
S OVP 225mV S SOFT-START REF 2V 0.4% PWM S/R PWM3
MAX8524 MAX8525
PWM
S/R
PWM2
REF S VID4 VID3 VID2 VID1 REF VID0 RU (MAX8525 ONLY) VID5 COMP CC RCS CS1+ RAPIDACTIVE AVERAGE CURRENT SENSE NO 7-BIT COUNTER LOAD DAC PWM S/R PWM4
OFFSET ROM
EQUAL?
1s DELAY
GMV
OPERATION MODE DETECT CS1_3GMC PHASE 1
RB
RSNS1
GMC PHASE 2 CS3+
RS+ RSDA RSBUF REF /2 CLAMP
GMC PHASE 3 CS2+
CS2_4GMC PHASE 4 CS4+ ONE OF FOUR PHASES DEPICTED GND ILIM
22
______________________________________________________________________________________
2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX8524/MAX8525
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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